FirePlace: Thermal-Aware Placement for 3D ICs

As conventional 2D integrated circuits approach scaling limits, 3D ICs provide a promising path toward higher integration density, shorter interconnects, and heterogeneous integration. However, vertical stacking also increases power density and strengthens thermal coupling across dies, making hotspot mitigation a first-order concern during physical design. Placement is a particularly important stage because macro and standard-cell locations shape both interconnect structure and the thermal profile of the final design.

In this work, we propose FirePlace, a two-stage thermal-aware placement framework for F2F-bonded 3D ICs. The framework combines mask-based macro placement with analytical standard-cell placement, aiming to reduce peak temperature while maintaining competitive wirelength.

Macro Placement

For macro placement, FirePlace introduces 3D PowerMask, a lightweight power-distribution-aware mask. It is combined with 3D WireMask to guide macros toward legal, thermally favorable locations while controlling wirelength degradation. This stage is important because high-power macros often dominate the early thermal landscape and strongly affect the remaining placement space for standard cells.

Standard-Cell Placement

For analytical standard-cell placement, FirePlace builds a compact thermal model based differentiable thermal objective. The thermal term is optimized together with bistratal wirelength and density objectives, allowing the placer to account for temperature during gradient-based optimization rather than treating thermal effects only as a post-placement check.

GPU Acceleration

Thermal evaluation can become a major runtime bottleneck. FirePlace precomputes and reuses the inverse thermal conductance matrix, and accelerates major differentiable placement operators on GPUs. In the reported experiments, the GPU implementation achieves an average per-iteration speedup of 33.576x, with especially large acceleration for the thermal operator.

Results

On ISPD 2005 full-flow cases, FirePlace reduces peak temperature by 12.5% on average and reduces temperature range by 30.4%, while maintaining competitive wirelength. Cell-only experiments further show that the proposed thermal-aware standard-cell placement improves thermal quality without sacrificing wirelength.

Takeaway

The key lesson is that thermal-aware 3D placement benefits from coordinated optimization across both macro placement and standard-cell placement. By combining power-aware macro guidance, differentiable thermal modeling, and GPU acceleration, FirePlace provides a practical placement framework for thermally challenging 3D IC designs.